1. Field of the Invention
The present invention relates to semiconductor integrated circuit fabrication, devices and methods, and, in particular, is directed toward the method of forming a unique silicide local interconnect structure that extends from an exhumed gate electrode.
2. Description of the Related Art
As is well known in the semiconductor processing industry, refractory silicides are often used to form local interconnects between circuit nodes in a semiconductor integrated circuit. In particular, when a refractory metal, for example titanium (Ti), is deposited flushly adjacent a silicon material and exposed to a sufficiently high temperature, the refractory metal will react with the silicon material to form a refractory silicide contact, for example titanium silicide (TiSi2). Since the resulting silicide contact has a relatively low sheet resistance, interconnects having silicide contacts can be formed with a reduced size, thereby enabling increased circuit density.
While silicides are very versatile as materials for forming interconnecting structures in integrated circuits, in some applications the suicides may poorly interconnect to particular semiconductor devices. For example, with some exhumed contact structures, the processing steps may result in the interconnect structure being undercut at an exposed region adjacent the exhumed contact which can result in either a higher resistance contact or an open contact which may be inadequate for a particular application.
For example, FIG. 1 illustrates a known exemplary method of forming a silicide local interconnect 200 in a typical semiconductor device. In particular, the device comprises a plurality of gate stacks 204 that are preformed with a gate oxide layer 212 deposited on a substrate 208, a polysilicon layer 214 deposited on the gate oxide layer 212, a laterally conducting tungsten silicide (WSix) layer 210 deposited on the polysilicon layer 214, and an insulating layer 216 deposited over the tungsten silicide layer 210.
In this example, the local interconnect 200 extends between an exhumed surface 202 of the gate stack 204a and a distally positioned active region 206 of the substrate 208. In particular, the exhumed surface 202 corresponds to the upper surface of the laterally conductive tungsten silicide layer 210 of the gate stack 204a and the active region 206 of the substrate 208 corresponds to a source/drain surface region of an isolated CMOS transistor.
To form the interconnect 200, a layer of refractory metal, such as titanium (Ti) 218 is deposited above the silicon substrate 208 so that the refractory metal layer 218 contacts both the exhumed surface 202 of the gate stack 204a and the active region 206 of the substrate 208. A masking layer 220 is then deposited over the refractory metal layer 218 and etched so as to define the extent of the local interconnect 200. The masking layer 220, which may comprise silicon, polysilicon, silicon rich tungsten silicide, or silicon oxynitride, also acts as a source of silicon to promote silicide formation along the length of the interconnect 200 during a subsequent annealing process. The device then undergoes the well-known high temperature annealing process which transforms the refractory metal into a silicide, such as titanium silicide (TiSi2), at the active region 206 of the substrate 208 and at the exhumed surface 202 of the gate stack 204a. The transformation of the refractory material into a silicide at these locations results in a desirable low resistance contact between the exhumed contact, the active area and the interconnect. Subsequently, a selective wet etching process is then used to remove exposed excess refractory metal and other exposed refractory metal byproducts. Thus, the remaining refractory material positioned underneath the masking layer 220 forms the local interconnect 200 having titanium silicide contacts 222 and 224 formed at the exhumed surface 202 of the gate stack 204a and active region 206 of the substrate 208 respectively.
However, FIG. 1 illustrates a common problem associated with this kind of interconnect. In particular, since the exhumed tungsten silicide surface 202 is often a relatively poor source of silicon and since the width of the exhumed surface 202 is often relatively small, an underproduction of titanium silicide during annealing at the exhumed surface 202 often results. Thus, the selective wet etching process often results in the silicide contact 222 having a very severe undercut 226, as shown in FIG. 1. Consequently, the resistance of the titanium silicide contact 222 formed at the exhumed surface 202 of the gate stack 204a may be relatively large. Thus, circuit performance may be compromised and production yields may be decreased. Moreover, such problematic local interconnects may limit the extent of selective wet cleans, which could impede the development of increasingly reduced circuit dimensions.
From the foregoing, it will be appreciated that there is a need for an improved method of forming local interconnects that extend from an exhumed surface of a gate stack. In particular, there is a need for an improved method that results in the contact formed at the exhumed surface of the gate stack having a decreased resistance. To this end, there is a need for the local interconnect to be formed such that undercutting of the material at the exhumed surface of the gate stack is substantially reduced. Furthermore, there is a need for such a local interconnect to be formed in a simple and, therefore, cost effective manner.